This invention relates to a semiconductor crystal oscillator circuit and more particularly to such an oscillator circuit employed in an integrated circuit electronic watch.
The present invention deals with a problem which is encountered in crystal oscillator circuits, particularly quartz crystal oscillator circuits, which have an inverter stage using complementary insulated field-effect transistor technology. This technology is also referred to as "C-MOS technology", with "C-MOS" being an abbreviation for "Complementary Metal Oxide Semiconductor". As a result of the technological development, instead of the oxide, other insulated-gate materials have also come into common use for the channel region so that "C-MOS" no longer involves a limitation to oxides employed as insulated-gate materials.
The aforementioned inverter stage consists of a p-channel transistor and an n-channel transistor which have their series-connected drain-source paths connected between ground and the ungrounded terminal of the supply-voltage source and whose gate electrodes are connected together and, via the crystal having a resistor shunted thereacross, to the common drain-drain node of the two complementary transistors. The two crystal electrodes are also each connected either to ground or to the ungrounded terminal of the supply-voltage source via one capacitor. These two capacitors, just as the crystal, are part of the oscillator's feedback network.
Such crystal oscillator circuits are disclosed in German Published Application (DT-OS) 2,153,828. The problem underlying the invention is that the sum of the values of the gate threshold voltages of the two transistors limits the minimum supply voltage in such a manner that at supply voltages below the sum of the values of the gate threshold voltages the oscillator circuit does not start. This disadvantage is particularly disturbing in the case of low supply voltages, e.g. in the 1-V (volt) range.